EMI/EMC Design — Pabst Electronics

EMC Must Be Designed In

EMC Failures Are Almost Always Preventable

EMC failures late in a product development program are among the most disruptive and expensive problems an engineering team can face. A product that fails emissions or immunity testing after the hardware is finalized may require fundamental changes to the PCB layout, filtering strategy, or enclosure design — changes that consume weeks of engineering time and delay product launch.

The root cause of most late-stage EMC failures is the same: EMC was not treated as a design discipline from the beginning. Stack-up selection, power distribution network design, signal routing practices, filtering placement, and protection circuit topology were determined without EMC in mind.

At Pabst Electronics, EMC is a design input. Our engineers have followed EMC pre-compliance and compliance test execution firsthand — we know how test setups are configured, how coupling networks inject disturbances, and where under-protected designs fail. That knowledge is applied to every design we produce.

IEC 61000-3-2 IEC 61000-3-3 IEC 61000-4-2 (ESD) IEC 61000-4-4 (EFT) IEC 61000-4-5 (Surge) IEC 61000-4-6 (CS) IEC 61000-4-11

EMC Design Layers

1

PCB Stack-Up SelectionLayer count, plane arrangement, and impedance control for EMC

2

Power Distribution NetworkDecoupling strategy, plane splits, return current paths

3

Filtering DesignCommon-mode chokes, ferrite beads, LC filters at all I/O interfaces

4

Protection Circuit DesignTVS, MOV, GDT — sized and placed for required immunity levels

5

Layout EMC ReviewReturn paths, slot avoidance, cable interface placement

6

Pre-Compliance Test PlanRealistic test plan based on first-hand test execution experience

📡 We Have Followed EMC Tests in Person

Our engineers have observed IEC 61000-4 immunity tests in practice — how ESD guns are applied, how EFT/burst coupling clamps are placed, how surge generators are connected, how conducted susceptibility test setups are configured. We have seen where designs fail and why. That practical knowledge is embedded in our design approach — it informs our protection circuit topology, our filtering strategy, our layout review process, and our pre-compliance test plans.

The result is a measurably higher first-pass success rate at the compliance laboratory, and a substantially lower risk of expensive late-stage redesign.

Standards We Design To

Emissions & Immunity — IEC 61000 Series

IEC 61000-3-2

Harmonic Current Emissions

Limits for harmonic current emissions injected into the public supply network. We design power supply topologies and PFC circuits that comply with Class A, B, C, or D limits as applicable, and evaluate compliance through simulation and measurement.

IEC 61000-3-3

Voltage Fluctuation & Flicker

Limits for voltage fluctuations and flicker caused by equipment connected to the public supply. We analyze load current profiles and design input circuits to comply with the steady-state and transient voltage change limits.

IEC 61000-4-2

Electrostatic Discharge (ESD)

ESD immunity to contact and air discharge at the required test levels. We design ESD protection circuits using TVS diodes, transient suppressors, and PCB layout techniques — and verify the protection strategy against the applicable test levels.

IEC 61000-4-4

Electrical Fast Transient / Burst (EFT/B)

EFT/B immunity requires effective common-mode filtering at all I/O interfaces and power supply inputs. We design common-mode choke and capacitor filter networks specifically for EFT/B performance and verify their effectiveness against the required test levels.

IEC 61000-4-5

Surge Immunity

Surge immunity is one of the most demanding IEC 61000-4 tests and a leading cause of field failures when protection is inadequate. We design surge protection circuits using MOVs, GDTs, and TVS diodes in coordinated topologies that provide effective protection at the required 1.2/50 µs open-circuit voltage and 8/20 µs short-circuit current levels.

IEC 61000-4-6 / 4-11

Conducted Susceptibility & Voltage Dips

Conducted RF immunity (IEC 61000-4-6) and voltage dip/interruption immunity (IEC 61000-4-11) require both filtering design and firmware robustness. We address both the hardware and firmware aspects of immunity to these disturbances.

Protection Circuit Engineering

Designed, Evaluated, and Verified

Protection circuits are not generic solutions. Their effectiveness depends on correct component selection, proper placement, and disciplined PCB layout.

⚡ TVS Diodes

Transient voltage suppressor selection for ESD and surge protection — clamping voltage, peak pulse power, response time, and capacitance evaluated for each interface.

🔵 MOV / Varistors

Metal oxide varistor selection for mains surge protection — energy rating, clamping voltage, and life expectancy analyzed against the surge test levels and expected operating environment.

💡 Gas Discharge Tubes

GDT selection for high-energy surge applications — spark-over voltage, impulse breakdown, and coordination with downstream protection components.

🌀 Common-Mode Chokes

Common-mode choke selection and placement for EFT/B and conducted RF immunity — impedance, saturation current, and differential-mode leakage inductance evaluated.

🔷 Ferrite Beads

Ferrite bead selection for signal and power line filtering — impedance profile, DC bias de-rating, and interaction with downstream capacitance analyzed for each application.

🔘 LC Filters

LC filter design for power supply EMI filtering — cutoff frequency, insertion loss, and common-mode/differential-mode performance evaluated against the applicable limits.

Need a Product That Passes EMC on the First Attempt?

Talk to our EMC engineers about your product. We will define the applicable requirements, design the protection and filtering strategy, and prepare your pre-compliance test plan.

Contact an EMC Engineer

EMI/EMC Design & Evaluation